Nick Rathfelder

Electrical Engineering Student

Chip Design | Digital Hardware | PCB Development

Nick Rathfelder

Academics

Education

University: University of Waterloo
Degree: BASc in Electrical Engineering
Expected Graduation: June 2027
Exchange: Universidad Carlos III de Madrid (UC3M), 4-month term
GPA: 3.83 / 4.00

Academic Honors

Spring 2026 (4A) - Term Distinction
Spring 2025 (3A) - Term Distinction
Fall 2024 (2B) - Term Distinction
Winter 2024 (2A) - Term Distinction

Design Team

UW Baja SAE

Designed and built the wire harness powering the brake lights, kill switches, and front differential

Relevant Coursework

ECE 445 - Integrated Digital Electronics (CMOS Design)
ECE 493 - AI/ML Hardware
ECE 318 - Communication Systems
ECE 340 - Electronic Circuits 2
ECE 375 - Electromagnetic Fields and Waves
ECE 373 - Radio Frequency and Microwave Circuits (Exchange)

Work Experience

IP Design Intern

Altera Corporation

Sep 2026 - Dec 2026

Developed calibration firmware and ran RTL simulations for high-speed memory interfaces

  • Implemented DDR memory calibration firmware, running and analyzing VCS RTL simulations to validate it against the design
  • Retargeted LPDDR5 calibration firmware and regression tests to LPDDR4 per JEDEC timing requirements, debugging 6 failing tests
VCS RTL Simulation Embedded Firmware DDR / LPDDR

FPGA Engineering Intern

Curtiss-Wright Defense Solutions

Sep 2025 - Dec 2025

Designed, simulated and tested FPGA-based systems supporting aerospace and defense technologies

  • Designed RTL for a UART debug interface exposing internal hardware states during restricted-access environmental testing
  • Integrated third-party IP and supported simulation and testing of FPGA designs for mission-critical aerospace and defense systems
Verilog FPGA UART

Controls and Electrical Engineering Intern

Musashi AI

Jan 2025 - Apr 2025

Developed and tested PLC-based control systems for automotive AI inspection systems

  • Updated electrical drawings and developed PLC/robot programs for AI automotive inspection machines
  • Upgraded the Automate 2025 tradeshow inspection cell to add onboard chatter inspection of automotive camshafts
PLC Solidworks

Electrical Engineering Intern

Martinrea International

Sep 2023 - Dec 2023

Contributed to continuous improvement of automotive assembly lines through AI inspection systems

  • Implemented an AI weld inspection system designed to cut cycle time by over 25%
  • Integrated GPIO-triggered serial messaging into the in-house weld inspection system, improving response time
Python Raspberry Pi

Process Engineering Intern

Stelco - Lake Erie Works

Jan 2023 - Apr 2023

Supported the analysis and optimization of steel manufacturing processes to improve efficiency and workplace safety

  • Built Power BI reports giving the Hot Strip Mill operating team visibility into daily operations
  • Began developing a MATLAB and PLC image-analysis tool to monitor slag buildup on basic oxygen furnace walls
MATLAB Power BI PLC

Key Technical Skills

The languages, tools, and equipment I use across digital design, circuits, and PCB work.

Programming Languages

SystemVerilog
Verilog
VHDL
C / Embedded C
C++
Python
TCL
Perl
MATLAB
ARM Assembly

Software & Design Tools

Cadence Virtuoso
Cadence AWR
Xilinx Vivado
Quartus Prime
VCS
ModelSim
Verilator
cocotb
Altium Designer
LTspice
SolidWorks

Hardware Skills

Circuit Design / Simulation
SMD & Through-hole Soldering
Reflow Soldering
Timing Analysis
PCB Layout

Test & Measurement

Oscilloscope
Logic Analyzer
Multimeter
Function Generator
Spectrum Analyzer
Vector Network Analyzer
LCR Meter

Microcontrollers & Boards

Xilinx Spartan FPGA
Altera Max 10 FPGA
STM32
ARM Cortex
Raspberry Pi

Protocols & Interfaces

UART
USB
I2C
JTAG
SPI

Projects

Runtime-configurable systolic array mode wave diagram
RTL / ML Hardware

Runtime-Configurable Systolic Array

Reduced-scale RTL accelerator for transformer attention, with runtime-switchable dataflow and on-chip operand reuse

Design & Verification

  • Designed RTL for a 4×4 INT8 systolic array with four runtime dataflow modes (output-stationary, weight-stationary, quantize, reload)
  • Built a 2D diagonal mode-wave register that staggers mode transitions without global mode routing
  • Enabled on-chip query reuse across fused attention tiles, saving 30 cycles per attention operation (1.147×)
  • Verified bit-exact against a Python golden model using cocotb and Verilator
  • Team project of five; I owned the RTL for the systolic array and mode-wave logic
SystemVerilog cocotb Verilator Vivado
Read Report
16-bit carry-lookahead adder schematic
CMOS / IC Design

16-bit CMOS Carry-Lookahead Adder

Transistor-level 16-bit adder with two-level carry lookahead, designed for 1 ns addition time across all corners

Design & Results

  • Built a 45 nm static CMOS adder from four 4-bit lookahead blocks and a second-level carry generator
  • Cut worst-case delay from 1008 ps to 456 ps versus a ripple-carry baseline at TT, 27 °C
  • Met the 1 ns spec at every process and temperature corner (676.5 ps worst case at SS, 85 °C)
  • Characterized delay, power, and power-delay product across test vectors and a supply voltage sweep
Cadence Virtuoso Static CMOS Corner Analysis PDP
Read Report
FFT Core
FPGA Design

FFT Core

Custom 1024-point decimation-in-time FFT core

Design & Verification

  • Designed iterative, 10-stage computation core for controlling a single complex butterfly unit
  • Implemented state machine for iteration and address generation
  • Pipelined output stream to be AXI4 stream compliant
  • Simulated DC, nyquist, and custom sinusoidal input signals using custom testbench
Xilinx Vivado Verilog TCL Simulation
View HDL Code
Electromagnetic Launcher
STM32 + PCB Design

Electromagnetic Launcher

Five-stage battery powered coilgun prototype

Key Features

  • Custom two layer PCB for interfacing with STM32 Black Pill
  • Implemented simple coil timing sequencing for firing mechanism on STM32
  • Designed and 3D printed all coil stages using Solidworks
  • Assembled and tested base functionality with simple wire harness
STM32 Altium SolidWorks C++
View Code
RF Reflectometer
RF/Microwave

RF Reflectometer

Dual output port RF reflectometer integrated on a full microstrip PCB

Development Process

  • Designed using a coupled microstrip directional coupler, a wilkinson divider and an RF amplifier
  • Generated full-layout PCB layout in Cadence AWR, utilizing small microstrips for all ports
  • Utilized de-embedding procedure to extract true reflection coefficient
  • Simulated with a 5% bandwidth centered at 3.5 GHz using Cadence AWR
Cadence AWR Layout Smith Chart De-embedding
Design File

Additional Projects

FPGA

UART Core + Debug Messager

Custom 115 200 baud UART core designed using a synchronous dual-clock FIFO, integrated into an FPGA debug messager

Xilinx Spartan 7 UART
FPGA

FPGA Traffic Light Controller

Sequential E-W and N-S traffic light controller designed using a custom mealy state machine

Altera Max 10 GPIO
Electrical

Water Reservoir Control System

STM32-based control system for automating the irrigation of three different zones on a user defined schedule

STM32 Breadboard
PCB

5V-12V Boost Converter PCB

5V-12V 2.5A switching boost converter PCB, featuring a power switch and an output indicator LED

Switching PSU PWM
PCB

AC-DC Dual Output Power Supply

Custom 120VAC to ±20VDC power supply designed using a power transformer, a full-wave rectifier and dual output regulators

Rectifier LDO

Portfolio & Resume

Complete Portfolio

Download my full portfolio PDF with detailed project documentation and technical work.

Download Portfolio

Resume

Download my one-page resume with a concise summary of my education, experience, and skills.

Download Resume

Get In Touch

Interested in collaborating or have a question? Feel free to reach out!

Prefer email? nhrathfe@uwaterloo.ca